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CPUs and Architecture

A central processing unit fetches an instruction from memory, decodes it, executes it, and writes the result. Then it does the same with the next...

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This Shipslides page presents CPUs and Architecture as an interactive HTML presentation deck in the Technology catalog with 32 slides. The share page keeps the uploaded deck sandboxed while exposing readable context, topics, and a slide outline for viewers and search engines.

A central processing unit fetches an instruction from memory, decodes it, executes it, and writes the result. Then it does the same with the next instruction. It does this several billion times a second, on a die smaller than a fingernail, dissipating less power than a light bulb. Key sections include: CPUs & Architecture.; Opening What a CPU is.; Chapter I Von Neumann.; Chapter II The transistor and Moore's law.; Chapter III The Intel 4004.; Chapter IV The x86 dynasty.; Chapter V RISC.; Chapter VI Pipelining.; Chapter VII Superscalar & out-of-order.; Chapter VIII Branch prediction..

Key sections

  • 01CPUs & Architecture.
  • 02Opening What a CPU is.
  • 03Chapter I Von Neumann.
  • 04Chapter II The transistor and Moore's law.
  • 05Chapter III The Intel 4004.
  • 06Chapter IV The x86 dynasty.
  • 07Chapter V RISC.
  • 08Chapter VI Pipelining.

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Slide outline
  1. 01CPUs & Architecture.
  2. 02Opening What a CPU is.
  3. 03Chapter I Von Neumann.
  4. 04Chapter II The transistor and Moore's law.
  5. 05Chapter III The Intel 4004.
  6. 06Chapter IV The x86 dynasty.
  7. 07Chapter V RISC.
  8. 08Chapter VI Pipelining.
  9. 09Chapter VII Superscalar & out-of-order.
  10. 10Chapter VIII Branch prediction.
  11. 11Chapter IX Cache hierarchy.
  12. 12Chapter X Cache coherence.
  13. 13Chapter XI SIMD.
  14. 14Chapter XII The multicore turn.
  15. 15Chapter XIII ARM.
  16. 16Chapter XIV Apple Silicon.
  17. 17Chapter XV RISC-V.
  18. 18Chapter XVI The GPU.
  19. 19Chapter XVII Nvidia.
  20. 20Chapter XVIII Spectre and Meltdown.
  21. 21Chapter XIX Power and thermals.
  22. 22Chapter XX Memory and DRAM.
  23. 23Chapter XXI The SoC.
  24. 24Chapter XXII TSMC and the foundries.
  25. 25Chapter XXIII Quantum and neuromorphic.
  26. 26Chapter XXIV AI accelerators.
  27. 27Chapter XXV Hennessy and Patterson.
  28. 28Chapter XXVI The next decade.
  29. 29Chapter XXVII Twenty essentials.
  30. 30Chapter XXVIII Watch & read.
  31. 31Chapter XXIX Names to know.
  32. 32The end of the deck.
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https://shipslides.com/d/technology-cpus-and-architecture
Category
Technology
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11.5 MB
Updated
2026-05-17
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https://shipslides.com/d/technology-cpus-and-architecture/llms.txt
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